---------------------------------------------------------------------------------
  -- Design Name : Register
  -- File Name   : GenReg32.vhd
  -- Function    : Simple 32b register file
  -- Authors     : Mirko Francuski  2006/0225
  --               Milos Mihajlovic 2006/0039
  -- School      : University of Belgrade
  --               School for Electrical Engineering
  --               Department for Computer Engineering and Information Theory
  -- Subject     : VLSI Computer Systems
---------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.UserPkg.all;

entity GenReg32 is
    port (
      clk:      in  std_logic;
      ld:       in  std_logic;
      cl:       in  std_logic;
      regIn:    in  word32;
      regOut:   out word32 := (others => '0')
    );
end GenReg32;

architecture behavioral of GenReg32 is
  signal data: word32 := (others => '0');

begin
  
  process(clk)
  begin
    if rising_edge(clk) then -- read
      regOut <= data;
    end if;  
          
    if falling_edge(clk) then -- write
      if (cl = '1') then
        data <= (others => '0');
      else
        if (ld = '1') then
          data <= regIn;
        end if;
      end if;
    end if;
  end process;

end architecture behavioral;
